The invention relates in general to a cathode ray tube controller to interface cathode ray tube (CRT) raster scan displays with a processor such as a microcomputer and in particular to a programmable display control module forming part of the controller for providing video timing controls for the CRT.
As with programming where the need to design very large programs dictated a structured approach, so the problems of VLSI lead to the search for structures logic arrays, the programmable logic array being the best example so far. In the display controller application there is a recurrent need to compare a pre-set value with a running count, for example to give cursor position, end of line, end of frame, etc.
The obvious approach is to load the required pre-set value into a register and use an exclusive OR function to provide an event match between the stored value and the system clock supplied over a suitable bus. This basic compare function is repeated as often as it is necessary. Most requirements will have two such structures for example one comparing a character count with a pre-set value and the other comparing a row count with another pre-set value. A logical AND of the two comparisons is used to give the event match. In a further requirement, the event match signal is used to set a latch and a similar repeated structure is provided to re-set the latch. All three of these arrangements are required many times over on a CRT controller chip and the eventual silicon layout is both inefficient and difficult to implement, change and test.
Typical of such integrated devices are the modern CRT controllers such as the Motorola MC 6845 CRT Controller; the Intel 8275 Programmable CRT Controller; and the Intel 8276 Small System CRT Controller.
The Motorola MC6845 CRT Controller (CRTC) is representative of the state-of-the art at the time that the present invention was made and is now briefly described. This CRTC performs the interface to raster scan CRT displays and provides video timing and refresh memory addressing. The CRTC consists of programmable horizontal and vertical timing generators, programmable linear address register, programmable cursor logic, light pen capture register, and control circuitry for interface to a processor bus. All CRTC timing is derived from a clock running at the character rate. Coincidence circuits continuously compare character counter contents with the contents of a number (eighteen) of programmable registers to provide, among other functions, horizontal timing (HSYNC), vertical timing (VSYNC), cursor location and size, etc. The processor communicates with the CRTC through a data bus into the register file of the CRTC and normally loads the CRTC registers sequentially from a firmware table during initialization after the power is turned on. The CRTC is provided as a single chip implemented using VLSI techniques.
Although a considerable improvement over the original controllers that used hard-wired gates to decode states represented by particular counts, these modern controllers suffer from two main disadvantages. The first disadvantage is that the complex combination of the various basic circuits required to perform the CRT timing control result in a complex cell topology. This generally results in an inefficient use of silicon when the chip is constructed. This leads directly to the second disadvantage in that once the complex topology of the cell has been determined and laid out in silicon then, generally speaking, it is not possible to change it without redesign of a new cell. Although there is some flexibility in that the pre-set values loaded in the registers can be changed during initialization, such implementations require all main features of the controller to be specified beforehand and designed in at the outset. If it is subsequently decided that an additional feature is required, then the chip must be redesigned with a new layout including the new feature. Naturally this is an extremely time consuming and often expensive operation.